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Timeline
Mendeley readers
Chapter title |
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
|
---|---|
Chapter number | 26 |
Book title |
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2002
|
DOI | 10.1007/3-540-45716-x_26 |
Book ISBNs |
978-3-54-044143-4, 978-3-54-045716-9
|
Authors |
Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal |
Mendeley readers
The data shown below were compiled from readership statistics for 8 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Belgium | 2 | 25% |
Unknown | 6 | 75% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Researcher | 3 | 38% |
Professor | 2 | 25% |
Student > Ph. D. Student | 1 | 13% |
Other | 1 | 13% |
Unknown | 1 | 13% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 5 | 63% |
Computer Science | 1 | 13% |
Biochemistry, Genetics and Molecular Biology | 1 | 13% |
Unknown | 1 | 13% |