Correct Hardware Design and Verification Methods
Springer Berlin Heidelberg
Chapter title |
Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs
|
---|---|
Chapter number | 6 |
Book title |
Correct Hardware Design and Verification Methods
|
Published by |
Springer, Berlin, Heidelberg, September 2001
|
DOI | 10.1007/3-540-44798-9_6 |
Book ISBNs |
978-3-54-042541-0, 978-3-54-044798-6
|
Authors |
Dirk Beyer |
Country | Count | As % |
---|---|---|
Germany | 1 | 10% |
Unknown | 9 | 90% |
Readers by professional status | Count | As % |
---|---|---|
Student > Ph. D. Student | 5 | 50% |
Professor | 1 | 10% |
Lecturer | 1 | 10% |
Student > Master | 1 | 10% |
Student > Postgraduate | 1 | 10% |
Other | 0 | 0% |
Unknown | 1 | 10% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 9 | 90% |
Unknown | 1 | 10% |